DocumentCode
3389880
Title
Methodology for multi-layer interdigitated power and ground network design
Author
Jakushokas, Renatas ; Friedman, Eby G.
Author_Institution
Dept. of Electr. & Comput. Eng., Univ. of Rochester, Rochester, NY, USA
fYear
2010
fDate
May 30 2010-June 2 2010
Firstpage
3208
Lastpage
3211
Abstract
Higher operating frequencies and greater power demands have increased the requirements on the power and ground network. Simultaneously, due to the larger current loads, current densities are increasing, making electromigration an important design issue. The optimal wire width for an interdigitated power and ground network is based on the resistive and inductive (both self- and mutual) impedance. In this paper, a methodology for optimizing a multi-layer interdigitated power and ground network is presented, reducing the current density and impedance of a network. Based on 65 nm, 45 nm, and 32 nm CMOS technologies, the optimal width as a function of metal layer is determined for different frequencies, suggesting important trends for interdigitated power and ground networks.
Keywords
CMOS integrated circuits; distribution networks; electromigration; CMOS technologies; current densities; current loads; electromigration; inductive impedance; multi-layer interdigitated ground network design; multi-layer interdigitated power network design; network impedance; resistive impedance; size 32 nm; size 45 nm; size 65 nm; CMOS technology; Current density; Electromigration; Frequency estimation; Impedance; Inductance; Network-on-a-chip; Packaging; Voltage; Wires;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Conference_Location
Paris
Print_ISBN
978-1-4244-5308-5
Electronic_ISBN
978-1-4244-5309-2
Type
conf
DOI
10.1109/ISCAS.2010.5537931
Filename
5537931
Link To Document