Title :
SEU testing of 32-bit microprocessors (for space application)
Author :
Velazco, R. ; Karoui, S. ; Chapuis, T.
Author_Institution :
Lab. de Genie Inf., Grenoble, France
Abstract :
Microprocessor sensitivity to the upset phenomenon has been generally evaluated by enumerating the bit modifications of programmer accessible registers, due to circuit irradiation with heavy-ions. For current 32-bit processors these registers represent only a little part of the sensible area. The authors´ work aims at comparing the upset cross-section obtained when the tested microprocessor is exercised with commonly used register tests, to those obtained using test programs that activate more thoroughly the circuit memory elements. Experimental results of upset tests performed on two different microprocessors. The MC 68020 and the SPARC MHS 90C601, and the corresponding floating-point coprocessors (the 68882 and the 90C602) are presented.
Keywords :
VLSI; aerospace instrumentation; aerospace simulation; integrated circuit testing; ion beam effects; microprocessor chips; radiation hardening (electronics); reduced instruction set computing; 32-bit microprocessors; MC 68020; RISC; SEU testing; SPARC MHS 90C601; VLSI; complex instruction set architecture; floating-point coprocessors; register tests; space electronics; upset cross-section; Application software; Circuit simulation; Circuit testing; Coprocessors; Digital systems; Microprocessors; Performance evaluation; Proton accelerators; Random access memory; Registers;
Conference_Titel :
Radiation Effects Data Workshop, 1992. Workshop Record., 1992 IEEE
Conference_Location :
New Orleans, LA, USA
Print_ISBN :
0-7803-0930-8
DOI :
10.1109/REDW.1992.247330
