Title :
Cycle time reduction at a major Texas Instruments wafer fab
Author :
Potti, Kishore ; Whitaker, Mark
Author_Institution :
DMOS 5 Wafer Fab, Texas Instrum. Inc., Dallas, TX, USA
fDate :
31 March-1 April 2003
Abstract :
This paper highlights the strategic and tactical applications of simulation modeling and how it was used to reduce cycle time at a major Texas Instruments wafer fab.
Keywords :
integrated circuit manufacture; Texas Instruments wafer fab; cycle time; semiconductor manufacturing; simulation model; Control systems; Data warehouses; Electronic mail; Instruments; Job shop scheduling; Production facilities; Qualifications; Routing; Semiconductor device modeling; Throughput;
Conference_Titel :
Advanced Semiconductor Manufacturing Conference and Workshop, 2003 IEEEI/SEMI
Print_ISBN :
0-7803-7681-1
DOI :
10.1109/ASMC.2003.1194477
