Title :
The influence of processing conditions on data retention behavior in a deep submicron NVM process
Author :
Karnett, M. ; Qian, S. ; Solis, R. ; Tao, X. ; Black, A. ; Boonsanguan, S. ; Liu, A.
Author_Institution :
Philips Semicond., San Antonio, TX, USA
fDate :
31 March-1 April 2003
Abstract :
Detailed investigations and process characterizations were performed to identify and resolve the source for programmed cell charge loss and data retention capability within the EPROM cells of our 0.35 μm Non-Volatile Memory (NVM) process technology. Both front- and back-end processing steps influenced the data retention behavior, with the most significant impact arising from the use of a high density plasma (HDP) oxide as the inter-metal dielectric. We postulate that cumulative charge buildup during processing lead to the severe charge retention effects observed and near zero yield at wafer probe.
Keywords :
CMOS memory circuits; EPROM; integrated circuit manufacture; plasma deposition; spin coating; 0.35 micron; EPROM cells; SOG; backend processing steps; cumulative charge buildup; data retention behavior; deep submicron NVM process; frontend processing steps; high density plasma oxide; inter-metal dielectric; nonvolatile memory process; processing conditions; programmed cell charge loss; severe charge retention effects; spin-on-glass; threshold voltage drift; Circuit testing; Dielectrics; EPROM; Nonvolatile memory; Plasma density; Plasma materials processing; Plasma sources; Probes; Threshold voltage; USA Councils;
Conference_Titel :
Advanced Semiconductor Manufacturing Conference and Workshop, 2003 IEEEI/SEMI
Print_ISBN :
0-7803-7681-1
DOI :
10.1109/ASMC.2003.1194479
