A 7-bit 16-MS/s low-power CMOS pipeline ADC

Author

Zhaodong, Zhuang ; Zhiqun, Li

Author_Institution

Sch. of Integrated Circuits, Southeast Univ., Nanjing, China

fYear

2011

fDate

25-28 Sept. 2011

Firstpage

1082

Lastpage

1085

Abstract

This paper describes a 7-bit 16MS/s CMOS pipeline ADC for the application of ZigBee receiver. A 2.5-bit/stage Multiplying DAC (MDAC) is designed to realize the pipeline ADC. Sample-and-hold amplifier (SHA)-less and operational transconductance amplifier (OTA)-sharing technique is adopted to save power dissipation. Dynamic comparator can be chosen to reduce the power dissipation. Designed in a TSMC 0.18μm CMOS process, a power dissipation of only 3.7 mW from a 1.8-V supply is achieved. The area of ADC core is 0.65mm×0.38mm, the post-simulation shows that SNDR and SFDR are 40.9dB and 48.6dB, when sampling 3.015625MHz sinusoid input signal at 16MHz sampling clock.

Keywords

CMOS integrated circuits; Zigbee; analogue-digital conversion; low-power electronics; operational amplifiers; radio receivers; sample and hold circuits; OTA-sharing technique; TSMC process; ZigBee receiver; analog-to-digital converter; dynamic comparator; frequency 16 MHz; frequency 3.015625 MHz; low-power CMOS pipeline ADC; multiplying DAC; operational transconductance amplifier; power 3.7 mW; power dissipation reduction; sample-and-hold amplifier-less technique; voltage 1.8 V; word length 2.5 bit; word length 7 bit; CMOS integrated circuits; Capacitors; Clocks; Operational amplifiers; Pipelines; Transistors; Wireless sensor networks; Comparator; Low-Power Dissipation; OTA-sharing; Pipeline ADC; ZigBee;

fLanguage

English

Publisher

ieee

Conference_Titel

Communication Technology (ICCT), 2011 IEEE 13th International Conference on

Conference_Location

Jinan

Print_ISBN

978-1-61284-306-3

Type

conf

DOI

10.1109/ICCT.2011.6158048

Filename

6158048