Bi-Layer Systolic Architecture for Bit-Serial Implementation of Discrete Wavelet Transform

In this paper, we present a bit-serial systolic architecture for computation of the discrete wavelet transform (DWT). The computations pertaining to the low-pass and high-pass filters of the recursive pyramid algorithm (RPA) are computed separately by two different layers in the proposed bi-layer structure. The structure is fully pipelined and requires a clocking period of only one full-adder delay. The hardware complexity of the proposed design is 58% of the existing bit-serial architecture up to 4-th level of decomposition with less than half of the computation time of the other