A multiplier with multiple error correction capability

This paper presents a technique for increasing the reliability of arithmetic units. An error model is then presented; this model we´ll represents the faulty behavior of many arithmetic units. The Residue Number System and its related properties are used in order to obtain a simple architecture (called Reliability Network, R-Net). The main characteristics of the presented technique are a significant reduction in the number of gales and a limited increase of global execution times. The extensive use of combinational logic makes it possible to implement the R-Net almost completely by means of Programmable Logic Arrays (PLA´s). Finally, both the intrinsic regularity of the R-Net and its simple internal interconnection scheme make this approach suitable for a practical VLSI implementation.