Title :
Systolic Architecture for Transposition-Free VLSI Implementation of Separable 2-D DWT
Author :
Mohanty, Basant K. ; Meher, Pramod K.
Author_Institution :
Dept. of Electron. & Commun. Eng., Jaypee Inst. of Eng. & Technol., Raghogarh
fDate :
Oct. 30 2006-Nov. 1 2006
Abstract :
In this paper, we present a novel systolic implementation of separable two-dimensional (2-D) discrete wavelet transform (DWT). Unlike the existing structures, the proposed design does not require any input/output network or additional hardware unit for transposition of intermediate output matrix. Consequently, it provides a significant saving of hardware and computation-time. It has 100% hardware utilization efficiency, and offers higher throughput rate with significantly less area-time complexity compared with the existing structures
Keywords :
VLSI; discrete wavelet transforms; systolic arrays; 2D DWT; VLSI implementation; discrete wavelet transform; systolic architecture; very large scale integration; Clocks; Computer architecture; Delay; Discrete wavelet transforms; Equations; Hardware; Low pass filters; Nonlinear filters; Two dimensional displays; Very large scale integration;
Conference_Titel :
Communication systems, 2006. ICCS 2006. 10th IEEE Singapore International Conference on
Conference_Location :
Singapore
Print_ISBN :
1-4244-0410-X
Electronic_ISBN :
1-4244-0411-8
DOI :
10.1109/ICCS.2006.301398
