The design of two easily-testable VLSI array multipliers

Array multipliers are well-suited for VLSI implementation because of the regularity in their iterative structure. However, most VLSI circuits are very difficult to test. This paper shows that, with appropriate cell design, array multipliers can be designed to be very easily-testable. An array multiplier is called C-testable if all its adder cells can be exhaustively tested while requiring only a constant number of test patterns. The testability of two well-known array multiplier structures are studied. The conventional design of the carry-save array multiplier is shown to be not C-testable. However, a modified design, using a modified adder cell, is generated and shown lo be C-testable and requires only 76 test patterns. Similar results are obtained for the Baugh-Wooley two´s complement array multiplier. A modified design of the Baugh-Wooley array multiplier is shown to be C-testable and requires 55 test patterns. The implementation of a practical C-testable 16 × 16 array multiplier is also presented.