Numerical limitations on the design of digit online networks

A fully digit online arithmetic unit generates at least the i most (least) significant digits of the result after having been supplied no more than the (i+k) most (least) significant digits of each operand, where k is a small constant. This digit serial property can be used to reduce the aggregate fill and flush times of a chained array of digit online arithmetic units and to reduce their VLSI interconnection complexity. However, because of this digit serial property, unique and inherent limitations may have to be imposed on any arithmetic unit which performs digit online operations. For some calculations, these limitations may be so severe as to make digit online evaluation virtually impossible. We show several important signal processing problems where these limitations have either been avoided or their effect greatly reduced.