A fine-resolution Time-to-Digital Converter for a 5GS/S ADC

Author

Townsend, Kenneth A. ; Macpherson, Andrew R. ; Haslett, James W.

Author_Institution

TRLabs., Univ. of Calgary, Calgary, AB, Canada

fYear

2010

fDate

May 30 2010-June 2 2010

Firstpage

3024

Lastpage

3027

Abstract

This paper presents the architecture of a high-speed time-based Analog-to-Digital Converter (ADC) based on voltage-to-time and time-to-digital conversion. A tunable Time-to-Digital Converter (TDC) that is robust against process variation and suitable for embedding within a 3-bit ADC is discussed and its performance evaluated. Simulation shows that when the TDC is designed in a 90nm CMOS process it is capable of a DNL and INL less than ±0.040L5B and ±0.015LSB, respectively, for 9mW of power consumption at 5GS/s with a 6.25ps resolution.

Keywords

CMOS integrated circuits; analogue-digital conversion; 3-bit ADC; CMOS process; fine-resolution time-to-digital converter; high-speed time-based analog-to-digital converter; time-to-digital conversion; tunable time-to-digital converter; voltage-to-time conversion; Analog-digital conversion; Clocks; Delay effects; Delay lines; Radio frequency; Robustness; Sampling methods; Signal resolution; Tunable circuits and devices; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on

Conference_Location

Paris

Print_ISBN

978-1-4244-5308-5

Electronic_ISBN

978-1-4244-5309-2

Type

conf

DOI

10.1109/ISCAS.2010.5538004

Filename

5538004