Fully integrated and reconfigurable architecture for coherent self-testing of IQ ADCs

Author

Santin, E. ; Oliveira, L.B. ; Nowacki, B. ; Goes, J.

Author_Institution

Univ. Nova de Lisboa, Capanca, Portugal

fYear

2010

fDate

May 30 2010-June 2 2010

Firstpage

1927

Lastpage

1930

Abstract

In this paper we present a reconfigurable architecture for coherent built-in self-testing (BIST) of high speed IQ ADCs with moderate resolutions. The proposed system can be fully integrated with the ADC and, besides a low-jitter clock reference, no other external high quality generators are required. A locked system comprising a first phase-locked loop (PLL) with two IQ linear outputs and a second PLL with a squared output signal are proposed as well as the dedicated voltage-controlled oscillator (VCO) circuits. To illustrate the simplicity of the proposed solution, the system is designed, parameterized and simulated targeting the BIST of a 6-bit 1 GS/s ADC.

Keywords

CMOS integrated circuits; analogue-digital conversion; built-in self test; clocks; integrated circuit testing; phase locked loops; reconfigurable architectures; IQ ADC; IQ linear output; coherent built-in self-testing; coherent self testing; fully integrated ADC; low jitter clock reference; phase locked loop; reconfigurable architecture; voltage controlled oscillator; Built-in self-test; Circuit testing; Clocks; Costs; Phase locked loops; Reconfigurable architectures; Sampling methods; Signal generators; Signal resolution; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on

Conference_Location

Paris

Print_ISBN

978-1-4244-5308-5

Electronic_ISBN

978-1-4244-5309-2

Type

conf

DOI

10.1109/ISCAS.2010.5538009

Filename

5538009