Title :
Timing driven multi-FPGA board partitioning
Author :
Burra, Raghu ; Bhatia, Dinesh
Author_Institution :
Dept. of Electr. & Comput. Eng., Cincinnati Univ., OH, USA
Abstract :
System level design is increasingly turning towards FPGAs to take advantage of their low cost and fast prototyping. In this paper we present a timing driven partitioning approach for an architecturally constrained multi-FPGA system. The partitioning approach uses path-based clustering based on the work by Dennis et al. (1995) and retiming. The board-level architecture is based on the PCB model consisting of four Xilinx 4013 FPGAs. The proposed algorithm has been tested on large scale real designs
Keywords :
circuit CAD; field programmable gate arrays; logic CAD; logic partitioning; timing; PCB model; Xilinx 4013 FPGAs; architecturally constrained system; board-level architecture; multi-FPGA board partitioning; path-based clustering; system level design; timing driven partitioning; Clustering algorithms; Costs; Field programmable gate arrays; Large-scale systems; Partitioning algorithms; Prototypes; System-level design; Testing; Timing; Turning;
Conference_Titel :
VLSI Design, 1998. Proceedings., 1998 Eleventh International Conference on
Conference_Location :
Chennai
Print_ISBN :
0-8186-8224-8
DOI :
10.1109/ICVD.1998.646609
