LV CMOS high speed analog multiplier

In this paper we propose a new low voltage high-speed CMOS composite transistor. This new transistor with a 3 dB bandwidth of 444 MHz; lowers supply voltage down to |V_t|+2V_{ds, sat} and extends input voltage operating range to 1.8 V with a 3 V supply. These features together with the two high input impedance terminals provided by the composite transistor leads to the design of a high-speed four quadrant analog multiplier. All simulations have been carried out using MOSIS 2 μm N-well process with a 8 V supply. The results show that the multiplier can operate with a maximum differential input of 1 V_pp and ω_{-3 dB} of 305 MHz.