A low-power VLSI architecture for the Viterbi decoder

Author

Ju, Wann-Shyang ; Shieh, Ming-Der ; Sheu, Ming-hwa

Author_Institution

Dept. of Electron. Eng., Nat. Yun-Lin Univ. of Sci. & Technol., Taiwan

Volume

2

fYear

1997

fDate

3-6 Aug. 1997

Firstpage

1201

Abstract

This paper presents a VLSI architecture for the Viterbi decoder aimed at reducing the average power dissipation based on the modified T-algorithm and the radix-2 butterfly module. Simulation results show that on the average, more than half of states at each time stage are not needed to be processed for the (4, 1, 6) convolutional code at bit error probability P_b≤10^-2. Therefore, significant power reduction can be achieved by reducing the total number of path metric computations and eliminating waste memory read/write operations. Based on the TSMC 0.6 um SPDM process and the Compass cell library, the resulting core size is 2761×2996 μm².

Keywords

VLSI; Viterbi decoding; convolutional codes; digital signal processing chips; error statistics; Compass cell library; TSMC SPDM process; Viterbi decoder; average power dissipation reduction; bit error probability; convolutional code; low-power VLSI architecture; modified T-algorithm; radix-2 butterfly module; Computational modeling; Computer architecture; Convolutional codes; Error probability; Hardware; Maximum likelihood decoding; Power dissipation; Power engineering and energy; Very large scale integration; Viterbi algorithm;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1997. Proceedings of the 40th Midwest Symposium on

Print_ISBN

0-7803-3694-1

Type

conf

DOI

10.1109/MWSCAS.1997.662295

Filename

662295