DocumentCode
3393249
Title
Yield enhancement techniques using neural network pattern detection
Author
Zinke, Kevin ; Nasr, Mary Beth ; Hicks, Alan ; Crawford, Martin ; Zawrotny, Robert
Author_Institution
Digital Equipment Corp., Hudson, MA, USA
fYear
1997
fDate
10-12 Sep 1997
Firstpage
211
Lastpage
215
Abstract
Neural network pattern recognition techniques for the detection of wafer and die level electrical failure patterns have been discussed in literature for many years. As a result of the research, many companies have written software to utilize neural network algorithms to provide pattern detection with varying degrees of success. Much of the original software, however, was not sufficiently automated to provide the users with adequate benefits to justify the cost and effort. Recent improvements in computer performance, programming techniques and the integration of statistics have created opportunities to utilize neural network pattern recognition with substantially less effort and cost. Analysis systems are now commercially available. This paper will look at the NEDA system available from DYM Corporation of Bedford Ma
Keywords
integrated circuit yield; neural nets; pattern recognition; semiconductor process modelling; NEDA; algorithm; automation; computer software; die level detection; electrical failure; neural network pattern recognition; statistics; wafer level detection; yield enhancement; Costs; Data analysis; Data engineering; Databases; Inspection; Neural networks; Optical filters; Pattern analysis; Pattern recognition; Probes;
fLanguage
English
Publisher
ieee
Conference_Titel
Advanced Semiconductor Manufacturing Conference and Workshop, 1997. IEEE/SEMI
Conference_Location
Cambridge, MA
ISSN
1078-8743
Print_ISBN
0-7803-4050-7
Type
conf
DOI
10.1109/ASMC.1997.630737
Filename
630737
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