A high-performance VLSI architecture for MAPS criterion motion estimation

Author

Shieh, Ming-Der ; Sheu, Ming-hwa ; Hsu, Yu-Chin ; Sheu, Jia-Lin

Author_Institution

Dept. of Electron. Eng., Nat. Yunlin Univ. of Sci. & Technol., Taiwan

Volume

2

fYear

1997

fDate

3-6 Aug. 1997

Firstpage

1221

Abstract

In this paper, a novel block-matching criterion called partitioned mean absolute error of projective sum (PMAPS) is proposed to reduce the computational complexity of block-based motion estimation. With approximate prediction quality and compression efficiency as the mean absolute difference (MAD), the PMAPS can save about 50% computational load of MAD by the fast algorithm presented. Based on its simple and regular properties, a versatile 1-D array architecture and its VLSI implementation are developed with the characteristics of 100% hardware utilization, simple control, and flexible and modular structures.

Keywords

VLSI; computational complexity; data compression; image matching; motion estimation; video coding; 1D array architecture; MAPS criterion; VLSI architecture; approximate prediction quality; block-matching criterion; compression efficiency; computational complexity; computational load; mean absolute difference; modular structures; motion estimation; partitioned mean absolute error of projective sum; Computational complexity; Computer architecture; Hardware; Motion estimation; Partitioning algorithms; Real time systems; Redundancy; Very large scale integration; Video compression; Videoconference;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1997. Proceedings of the 40th Midwest Symposium on

Print_ISBN

0-7803-3694-1

Type

conf

DOI

10.1109/MWSCAS.1997.662300

Filename

662300