An image processing hardware design environment

Verilog HDL and XV is used to create an image processing design environment. The traditional HDL design simulation process where expected signal values are compared to those generated by the simulator is not sufficient, efficient, nor adequate to design and verify an image processing application hardware system for rapid implementation; e.g., using FPGAs. With a scalable image processing hardware architecture and the new design environment, rapid HDL modeling and simulation of image processing applications is feasible.