• DocumentCode
    3393662
  • Title

    Is quality a design constraint for sub 100nm designs?

  • Author

    Ohr, Steven ; Chatterjee, Pallab

  • Author_Institution
    EETimes
  • fYear
    2003
  • fDate
    24-26 March 2003
  • Firstpage
    15
  • Lastpage
    17
  • Keywords
    Costs; Electronic design automation and methodology; Job design; Job shop scheduling; Life testing; Manufacturing processes; Materials testing; Packaging; Semiconductor device modeling; Silicon;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Quality Electronic Design, 2003. Proceedings. Fourth International Symposium on
  • Conference_Location
    San Jose, CA, USA
  • Print_ISBN
    0-7695-1881-8
  • Type

    conf

  • DOI
    10.1109/ISQED.2003.1194700
  • Filename
    1194700
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3393662