Title :
Is quality a design constraint for sub 100nm designs?
Author :
Ohr, Steven ; Chatterjee, Pallab
Author_Institution :
EETimes
Keywords :
Costs; Electronic design automation and methodology; Job design; Job shop scheduling; Life testing; Manufacturing processes; Materials testing; Packaging; Semiconductor device modeling; Silicon;
Conference_Titel :
Quality Electronic Design, 2003. Proceedings. Fourth International Symposium on
Conference_Location :
San Jose, CA, USA
Print_ISBN :
0-7695-1881-8
DOI :
10.1109/ISQED.2003.1194700
