Noise-aware driver modeling for nanometer technology

With the semiconductor industry evolving into the deep sub-micron (DSM) era, crosstalk noise becomes a critical issue that needs to be handled efficiently and accurately. Modern designs like system-on-chips have millions of noise-prone wires that need to be analyzed. Analysis using circuit-level simulation is not feasible. Efficient static noise analysis, which statically estimate noise based on linear circuit model, is widely used. However, traditionally drivers´ holding resistances are pre-characterized without considering the crosstalk noise. The driver´s holding resistance changes dramatically with the crosstalk noise induced voltage changing on the victim wire. For accurate noise estimation, the driver´s substantial nonlinear variation cannot be ignored. In this paper, we propose a novel method, which uses layout extracted parameters of coupling interconnect and pre-characterized parameters of driver to calculate an effective holding resistance. The noise-aware effective holding resistance dramatically improves the accuracy for noise magnitude and energy estimation. The proposed method is simple and efficient. It enables fast on-the-fly calculation of the effective holding resistance. Experiments show significant improvement in accuracy with almost negligible computation overhead.