A modern approach to digital fault simulation

Author

Erath, Paul ; Loretz, Robert

Author_Institution

Grumman Electron. Syst., Bethpage, NY, USA

fYear

1989

fDate

25-28 Sep 1989

Firstpage

118

Lastpage

123

Abstract

Benchmark testing has demonstrated the reality of significant throughput runtime improvement in simulation performance, when integrating the LOGOS DATPG (digital automatic test program generator) with a hardware accelerator. This new capability enables LOGOS to address current and future TPS (test program set) development problems associated with CPU intensive network model simulation. It is noted that the benefit derived from the simulation performance, observed in the integrated system, can be translated by TPS program managers into a cost-effective boiler plate for TPS development program proposals and estimates concerning computing resources and engineering manpower requirements

Keywords

application specific integrated circuits; automatic test equipment; automatic testing; circuit analysis computing; computer architecture; digital simulation; electronic equipment testing; fault location; ASIC; ATE; CPU intensive network model simulation; LOGOS DATPG; benchmark testing; cost-effective boiler plate; digital automatic test program generator; digital fault simulation; hardware accelerator; test program set; throughput runtime; Automatic programming; Automatic testing; Benchmark testing; Computational modeling; Engineering management; Hardware; Life estimation; Resource management; Runtime; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

AUTOTESTCON '89. IEEE Automatic Testing Conference. The Systems Readiness Technology Conference. Automatic Testing in the Next Decade and the 21st Century. Conference Record.

Conference_Location

Philadelphia, PA

Type

conf

DOI

10.1109/AUTEST.1989.81108

Filename

81108