DocumentCode
3394222
Title
Advanced module packaging method
Author
Salmon, Peter C.
Author_Institution
SysFlex, Los Altos, CA, USA
fYear
2003
fDate
24-26 March 2003
Firstpage
223
Lastpage
228
Abstract
An intermediate solution between conventional printed circuit board technology and wafer level packaging, WLP, is to fabricate interconnection circuits and flip chip assembly structures on large glass substrates using LCD manufacturing equipment. Trace widths of 5 microns and a trace pitch of 10 microns are achievable on flexible substrates as large as 1800×1500 mm. Back planes for displays and keyboards can also utilize thin film transistors, TFTs, as developed for LCDs and enhanced for flexible assemblies (200°C processing). A flexible circuit is built on a glass carrier with an intermediate release layer. The carrier is discarded after all processing is complete, including interconnection circuits, IC chip assembly, test and rework. The assembly method uses gold stud bumps on IC chips, and corresponding wells filled with solder on the motherboard 100-micron pad pitch is achievable for IC chips, module cables, and test connections. Avoidance of epoxy under layers contributes to a robust capability for reworking defective IC chips. The methods are applicable to a wide range of products, from cell phones to blade servers.
Keywords
flip-chip devices; integrated circuit interconnections; integrated circuit packaging; modules; substrates; 100 micron; 200 degC; 5 micron; IC chip assembly; LCD manufacturing equipment; TFT; advanced module packaging; blade server; conventional printed circuit board technology; flexible assembly; flexible circuit; flexible substrates; flip chip assembly structures; glass substrates; interconnection circuits; intermediate release layer; module cables; motherboard; solder; test connections; thin film transistors; wafer level packaging; Assembly; Circuit testing; Flexible printed circuits; Glass; Integrated circuit interconnections; Integrated circuit testing; Packaging; Substrates; Thin film transistors; Wafer scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Quality Electronic Design, 2003. Proceedings. Fourth International Symposium on
Print_ISBN
0-7695-1881-8
Type
conf
DOI
10.1109/ISQED.2003.1194735
Filename
1194735
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