Title :
Electrical and thermal analysis for system-in-a package (SiP) implementation platform
Author :
Wang, Michael ; Suzuki, Katsuharu ; Dai, Wayne
Author_Institution :
Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA
Abstract :
This paper presents an electrical and thermal performance analysis of system-in-a-package (SiP) memory/logic implementation platform based on chip-laminate-chip (CLC) technology. Internal IO interface inside CLC module has been modeled and compared with stack-chip (SC) implementation. Thermal analysis, including comparison against stack-chip and system-on- a-chip (SoC) is also presented. It is demonstrated that CLC technology provides significant performance advantage over conventional SiP technologies and has great impact on future system-level integration.
Keywords :
integrated circuit packaging; laminates; system-on-chip; thermal analysis; chip laminate chip; chip laminate chip module; electrical analysis; internal IO interface; memory/logic implementation platform; stack chip; system in a package; system level integration; thermal analysis; CMOS logic circuits; CMOS technology; Chip scale packaging; Costs; Fabrication; Laminates; Performance analysis; Random access memory; System-on-a-chip; Thermal conductivity;
Conference_Titel :
Quality Electronic Design, 2003. Proceedings. Fourth International Symposium on
Print_ISBN :
0-7695-1881-8
DOI :
10.1109/ISQED.2003.1194736
