DocumentCode :
3394263
Title :
Modeling and analysis of power distribution networks for gigabit applications
Author :
Beyene, Wendemagegnehu ; Yuan, Chuck ; Kim, Joong-Ho ; Swaminathan, Madhavan
Author_Institution :
Rambus Inc., Los Altos, CA, USA
fYear :
2003
fDate :
24-26 March 2003
Firstpage :
235
Lastpage :
240
Abstract :
As the operating frequency of digital systems increases and voltage swing decreases, it becomes increasingly important to accurately characterize and analyze power distribution networks (PDN). This paper presents the modeling, simulation, and measurement of a PDN in a high-speed FR4 printed circuit board (PCB) designed for chip-to-chip communication at a data rate of 3.2 Gbps and above. The test board consists of two transceiver chips placed on wire bond plastic ball grid array (PBGA) packages. The applied analysis method is a hybrid technique that combines the interactions of the power planes, interconnects, and the nonlinear drivers. The power planes and interconnects are modeled using the transmission matrix method (TMM) and rational interpolation, respectively. Then macro modeling is applied to generate reduced-order models to efficiently analyze the whole system including the nonlinear drivers using conventional circuit simulation tools such as SPICE. The transfer characteristics of the power planes are calculated and the effects of the decoupling capacitors and power supply noise are studied. The simulation results are also correlated with measurement data to verify the validity of the method.
Keywords :
ball grid arrays; circuit simulation; driver circuits; integrated circuit interconnections; integrated circuit modelling; interpolation; plastic packaging; printed circuits; transceivers; transmission line matrix methods; 3.2 Gbit/s; PCB; SPICE; chip-to-chip communication; conventional circuit simulation tools; decoupling capacitors; digital systems; gigabit applications; high speed FR4 printed circuit board; interconnects; macro modeling; nonlinear drivers; operating frequency; power distribution networks; power planes; power supply noise; rational interpolation; reduced order models; test board; transceiver chips; transfer characteristics; transmission matrix method; voltage swing; wire bond plastic ball grid array; Circuit simulation; Digital systems; Driver circuits; Frequency; Integrated circuit interconnections; Power system interconnection; Power system modeling; Power systems; Semiconductor device measurement; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Quality Electronic Design, 2003. Proceedings. Fourth International Symposium on
Print_ISBN :
0-7695-1881-8
Type :
conf
DOI :
10.1109/ISQED.2003.1194737
Filename :
1194737
Link To Document :
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