• DocumentCode
    3394394
  • Title

    Fast arithmetic on Xilinx 5200 FPGA

  • Author

    Laurent, B. ; Bosco, G. ; Saucier, G.

  • Author_Institution
    Inst. Nat. Polytech. de Grenoble, France
  • fYear
    1998
  • fDate
    4-7 Jan 1998
  • Firstpage
    322
  • Lastpage
    325
  • Abstract
    In this paper, classical adder and multiplier architectures applied to the Xilinx XC5200 FPGA are compared. To inherit advantages of both structural and algorithmic approaches, hybrid solutions are proposed such that the optimal trade-off between architectures and technology is reached. The resulting schemes yield optimized performance after the use of Xilinx place and route tools
  • Keywords
    VLSI; adders; digital arithmetic; field programmable gate arrays; multiplying circuits; parallel algorithms; Xilinx 5200 FPGA; Xilinx place/route tools; adder architectures; arithmetic algorithms; hybrid scheme; multiplier architectures; performance optimisation; Acceleration; Arithmetic; Concurrent computing; Delay; Equations; Field programmable gate arrays; Libraries; Logic devices; Multiplexing; Table lookup;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design, 1998. Proceedings., 1998 Eleventh International Conference on
  • Conference_Location
    Chennai
  • ISSN
    1063-9667
  • Print_ISBN
    0-8186-8224-8
  • Type

    conf

  • DOI
    10.1109/ICVD.1998.646626
  • Filename
    646626
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3394394