A cellular architecture for self-assembled 3D computational devices

To overcome physical size limitations in scaling transistors in inherently two-dimensional geometries, efforts are being directed at wafer stacking to implement more quasi three-dimensional (3D) architectures. However, significant and unprecedented gains in terms of packing and speed can be achieved if CMOS components can be integrated in truly 3D cellular porous architectures. In this paper, we present our initial results to create prototype 3D cellular computational devices by self-assembly. We first describe the cellular computational architecture based on Cell Matrix, an inherently defect and fault-tolerant architecture that is self-configurable, and therefore is ideally suited for ultra large-scale integration (ULSI). We then show first prototypes of functional polyhedral computational integrated devices at the centimeter and millimeter scales as a step toward self-folding porous crystal structures at the nanoscale. Our approach is rooted in the synergy between experiments, computation, and theory. It has the potential to address the major challenges of 3D integration: self-assembly, self-configuration, defect-tolerance, and cooling.