Design of 8T-nanowire RAM array

SRAM based memory blocks constitute a major part of state-of-art processor architectures. Increasing complexity and variation in nanometer CMOS fabrication has prompted exploration of memory circuits based on emerging nanofabrics. In this work, we propose a new 8T-Nanowire based RAM (8T-NWRAM) circuit for high density memory arrays. The design is based on N³ASIC, a nanofabric using combination of crosspoint nanowire FETs and integration with metal interconnects. The layout implementation is optimized to reduce bitline load and achieve high performance. The upper bound on bitcell area is 0.1μm², which is 50% more compared to conventional 6T-SRAM. However, both performance and leakage are significantly improved. Circuit simulation using N³ASIC 2C-xnwFET device models show improvements of >2X in read time and ~4X in write time compared to high performance SRAM. The average leakage power at 0.2nW is ~20X smaller compared to high performance SRAM. In comparison with existing 10T-NWRAM, the 8T-NWRAM provides a twofold improvement in read time and ~46% faster write time, but at the expense of ~30% increase in area and average leakage power. Thus, 8T-NWRAM is a viable alternative to 10T-NWRAM for performance vs area/leakage design requirement. We also study the impact of supply noise induced clock jitter on NWRAM circuits and propose adequate design margin to ensure bitcell stability.