VLSI implementation of a 300-MHz 0.35-μm CMOS 32-bit auto-reloadable binary synchronous counter with optimal test overhead delay

Author

Misra, S.K. ; Kolagotia, R.K. ; Srinivas, H.R. ; Mo, J.C. ; Diamondstein, M.S.

Author_Institution

AT&T Bell Labs., Allentown, PA, USA

fYear

1998

fDate

4-7 Jan 1998

Firstpage

326

Lastpage

329

Abstract

We describe the VLSI implementation of a fully testable high-speed binary synchronous counter that is pre-loadable and auto-reloadable. High-speed operation is achieved by precomputing the carry independent terms and by using the carry signal as a selector in the last gate before the storage latch. An efficient test logic is used that has minimal impact on the counter speed during normal operation, and significantly reduces the test time and test cost

Keywords

CMOS logic circuits; VLSI; counting circuits; delays; integrated circuit testing; logic testing; 0.35 micron; 300 MHz; 32 bit; CMOS binary synchronous counter; VLSI implementation; auto-reloadable counter; carry independent terms; fully testable counter; high-speed operation; optimal test overhead delay; pre-loadable counter; test logic; CMOS technology; Costs; Counting circuits; Delay; Digital signal processors; Frequency conversion; Logic arrays; Logic testing; Multiplexing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, 1998. Proceedings., 1998 Eleventh International Conference on

Conference_Location

Chennai

ISSN

1063-9667

Print_ISBN

0-8186-8224-8

Type

conf

DOI

10.1109/ICVD.1998.646627

Filename

646627