DocumentCode
3394747
Title
On the accuracy of return path assumption for loop inductance extraction for 0.1 μm technology and beyond
Author
Kim, SoYoung ; Massoud, Yehia ; Wong, S. Simon
Author_Institution
Center for Integrated Syst., Stanford Univ., CA, USA
fYear
2003
fDate
24-26 March 2003
Firstpage
401
Lastpage
404
Abstract
The most common assumption for chip-level inductance extraction is to restrict the current return path to the closest power or ground lines. This paper shows that this assumption is not necessarily valid for technologies beyond 0.1 μm. The actual inductance can exceed twice the value that is extracted from the model considering only the nearest current return paths. Analytical formulae to predict the worst case self inductance are proposed to deal with the errors that result from this assumption. These equations can be used as metrics to decide the size of inductance extraction window for future CAD tools.
Keywords
inductance; integrated circuit interconnections; integrated circuit modelling; 0.1 micron; CAD tools; chip level inductance extraction; ground lines; loop inductance; return path assumption; self inductance; Circuit noise; Circuit simulation; Computational modeling; Equations; Frequency; Inductance; Performance analysis; Timing; Wires; Working environment noise;
fLanguage
English
Publisher
ieee
Conference_Titel
Quality Electronic Design, 2003. Proceedings. Fourth International Symposium on
Print_ISBN
0-7695-1881-8
Type
conf
DOI
10.1109/ISQED.2003.1194766
Filename
1194766
Link To Document