Adaptive test clock scheme for low transition LFSR and external scan based testing

Author

Sivanantham, S. ; Gopakumar, G. ; Pandey, Ashutosh ; Paikada, M.J.

Author_Institution

Sch. of Electron. Eng., VIT Univ., Vellore, India

fYear

2013

fDate

4-6 Jan. 2013

Firstpage

1

Lastpage

5

Abstract

This paper presents an approach to reduce the test time of an external test applied from an automatic test equipment by speeding up low activity cycles, keeping the power under control. Based on the signal transitions, which are used to control the power consumption of the Circuit under test, the clock frequency can be varied. Two different methods have been considered for controlling the scan clock frequency: using hardware control and using pre-simulated and stored test data where a dynamically controlled scan clock is used.

Keywords

automatic test equipment; automatic testing; built-in self test; clocks; design for testability; logic design; logic testing; low-power electronics; shift registers; adaptive test clock scheme; automatic test equipment; circuit under test; dynamically controlled scan clock frequency; external scan-based testing; hardware control; linear feedback shift register; low-activity cycles; low-transition LFSR; power consumption control; presimulated test data; signal transitions; stored test data; test time reduction; Built-in self-test; Clocks; Frequency control; Hardware; Time frequency analysis; Vectors; Automatic Test Equipment; Built-in Self Test; Circuit Under Test; Design for testability; Integrated circuits; Linear Feedback Shift Register;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Communication and Informatics (ICCCI), 2013 International Conference on

Conference_Location

Coimbatore

Print_ISBN

978-1-4673-2906-4

Type

conf

DOI

10.1109/ICCCI.2013.6466280

Filename

6466280