• DocumentCode
    3394863
  • Title

    An embedded IDDQ testing architecture and technique

  • Author

    Tsiatouhas, Y. ; Haniotakis, Th ; Arapoyanni, A.

  • Author_Institution
    Dept. of Comput. Sci., Ioannina Univ., Greece
  • fYear
    2003
  • fDate
    24-26 March 2003
  • Firstpage
    442
  • Lastpage
    445
  • Abstract
    In this paper an embedded IDDQ testing architecture is presented that targets to overcome the excessive hardware overhead requirements in built-in current sensing based testing applications. Moreover, a technique that utilises the IEEE 1149.1 boundary scan standard to control the proposed architecture is provided. The proposed solution is characterised by low silicon area requirements and permits the application of IDDQ testing also in case that the chip is mounted on a printed circuit board.
  • Keywords
    IEEE standards; boundary scan testing; built-in self test; design for testability; integrated circuit testing; IEEE 1149.1 boundary scan standard; built in current sensing; embedded IDDQ testing architecture; hardware overhead requirements; printed circuit board; silicon area requirements; Circuit testing; Computer architecture; Computer science; Design for testability; Embedded computing; Leakage current; Power supplies; Silicon; Telecommunication computing; USA Councils;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Quality Electronic Design, 2003. Proceedings. Fourth International Symposium on
  • Print_ISBN
    0-7695-1881-8
  • Type

    conf

  • DOI
    10.1109/ISQED.2003.1194773
  • Filename
    1194773
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3394863