DocumentCode
3394911
Title
Linear bilateral CMOS resistor for neural-type circuits
Author
Sellami, L. ; Singh, S.K. ; Newcomb, R.W. ; Moon, G.
Author_Institution
Dept. of Electr. Eng., Maryland Univ., College Park, MD, USA
Volume
2
fYear
1997
fDate
3-6 Aug. 1997
Firstpage
1330
Abstract
A previous CMOS bilateral linear resistor is analyzed and shown to be reducible from four to two transistors with improved linearity. This is developed for neural-type circuits to allow its use in emulating both excitatory and inhibitory voltage variable synapses. Simulation results using parameters of MOSIS transistors are presented to verify the theory.
Keywords
CMOS analogue integrated circuits; VLSI; analogue processing circuits; neural chips; resistors; MOSIS transistors; excitatory voltage variable synapse; inhibitory voltage variable synapse; linear bilateral CMOS resistor; linearity; neural-type circuits; Batteries; Circuit simulation; Laboratories; MOS devices; MOSFETs; Moon; Resistors; Uniform resource locators; Very large scale integration; Voltage control;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1997. Proceedings of the 40th Midwest Symposium on
Print_ISBN
0-7803-3694-1
Type
conf
DOI
10.1109/MWSCAS.1997.662327
Filename
662327
Link To Document