Title :
Low power/minimum transistor building blocks for the implementation of back-propagation algorithms
Author :
Meléndez-Rodríguez, Miguel ; Silva-Martínez, José
Author_Institution :
Integrated Circuits Design Group, NBational Inst. of Astrophys. Optics & Electronics, Puebla, Mexico
Abstract :
Several building blocks intended for on-chip learning neural networks are proposed. The current based elements are adders, multipliers, activation functions and their derivatives. The priorities for the design are both minimum power consumption and minimum silicon area. Simulated results for two networks are reported.
Keywords :
VLSI; adders; backpropagation; integrated circuit layout; multiplying circuits; neural chips; VLSI; activation functions; adders; back-propagation algorithms; current based elements; multipliers; on-chip learning neural networks; power consumption; silicon area; Adders; Astrophysics; Circuit analysis; Energy consumption; Equations; Network-on-a-chip; Neural networks; Signal processing algorithms; Silicon; Voltage;
Conference_Titel :
Circuits and Systems, 1997. Proceedings of the 40th Midwest Symposium on
Print_ISBN :
0-7803-3694-1
DOI :
10.1109/MWSCAS.1997.662328
