DocumentCode :
3394950
Title :
Simulation and synthesis of VLSI communication systems
Author :
Jain, Rajeev ; Chien, Charles ; Cohen, Etan ; Ho, Leader
Author_Institution :
Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
fYear :
1998
fDate :
4-7 Jan 1998
Firstpage :
336
Lastpage :
341
Abstract :
This paper describes CAD tools for communication system design. The tools allow for rapid algorithm development using a functional model library and scripting procedures that automate iterative optimization of algorithm parameters. Implementation tools are linked into the algorithm design environment to allow efficiency in generating hardware designs from algorithm descriptions. Examples from channel coding and from modern design illustrate how the data flow simulation in the CAD environment can be exploited for simulating and designing each of these components
Keywords :
VLSI; channel coding; circuit CAD; circuit analysis computing; circuit optimisation; digital signal processing chips; iterative methods; modems; processor scheduling; telecommunication computing; telecommunication equipment; CAD environment; CAD tools; VLSI communication systems; algorithm design environment; algorithm parameters; channel coding; data flow simulation; functional model library; hardware design generation; implementation tools; iterative optimization; modern design; rapid algorithm development; scripting procedures; Algorithm design and analysis; Design automation; Design optimization; Hardware; Iterative algorithms; Libraries; Logic design; Modems; Signal processing algorithms; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design, 1998. Proceedings., 1998 Eleventh International Conference on
Conference_Location :
Chennai
ISSN :
1063-9667
Print_ISBN :
0-8186-8224-8
Type :
conf
DOI :
10.1109/ICVD.1998.646629
Filename :
646629
Link To Document :
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