• DocumentCode
    3395293
  • Title

    High speed test structures for in-line process monitoring and model calibration [CMOS applications]

  • Author

    Ketchen, Mark ; Bhushan, Manjul ; Pearson, Dale

  • Author_Institution
    IBM Res. Div., Yorktown Heights, NY, USA
  • fYear
    2005
  • fDate
    4-7 April 2005
  • Firstpage
    33
  • Lastpage
    38
  • Abstract
    The use of in-line test structures for routinely monitoring various high frequency aspects of the performance of CMOS gates is described. These compact test structures use DC I/Os and are compatible with standard parametric testers. The specific examples described are ring oscillators for a wide range of self-consistent parameter extraction ranging from circuit delays to gate length and leakage components; and a new class of self-timed/calibrated structure of which a circuit for measuring SOI switching history effects, utilizing 100 ps time-scale self-generated pulses, is presented as a representative example.
  • Keywords
    CMOS integrated circuits; calibration; integrated circuit testing; logic gates; process monitoring; 100 ps; CMOS gates; DC I/O test structures; SOI switching history effects; circuit delays; gate length; high speed test structures; in-line process monitoring; leakage components; model calibration; parametric testers; ring oscillators; self-consistent parameter extraction; self-generated pulses; self-timed calibrated structure; CMOS process; Calibration; Circuit testing; Delay effects; Frequency; Monitoring; Parameter extraction; Pulse measurements; Ring oscillators; Semiconductor device modeling;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Microelectronic Test Structures, 2005. ICMTS 2005. Proceedings of the 2005 International Conference on
  • Print_ISBN
    0-7803-8855-0
  • Type

    conf

  • DOI
    10.1109/ICMTS.2005.1452212
  • Filename
    1452212