Impact of mask alignment on the tunneling field effect transistor (TFET)

Author

Nirschl, Th ; Schaper, U. ; Einfeld, J. ; Henzler, St. ; Sterkel, M. ; Singer, J. ; Fulde, M. ; Hansch, W. ; Georgakos, G. ; Schmitt-Landsiedel, D.

Author_Institution

Inst. for Tech. Electron., Tech. Univ. Munich, Germany

fYear

2005

fDate

4-7 April 2005

Firstpage

43

Lastpage

46

Abstract

The tunneling field effect transistor (TFET) is a standard CMOS process flow compatible device which shows improved short channel characteristics and lower static power consumption. The device is generated by the p-implant layer overlapping the source extension. A test-structure is proposed to investigate the impact of the alignment of the p-implant mask on the device characteristics.

Keywords

doping profiles; field effect transistors; masks; semiconductor device measurement; tunnelling; CMOS process flow compatible device; TFET; low static power consumption; p-implant mask alignment; quantum-mechanical device; short channel characteristics; source extension overlapping p-implant layer; tunneling field effect transistor; CMOS process; CMOS technology; Charge carrier density; Diodes; Electrons; Energy consumption; FETs; MOSFET circuits; Testing; Tunneling;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures, 2005. ICMTS 2005. Proceedings of the 2005 International Conference on

Print_ISBN

0-7803-8855-0

Type

conf

DOI

10.1109/ICMTS.2005.1452216

Filename

1452216