DocumentCode :
3395541
Title :
Design and analysis of a TB/sec memory system
Author :
Beyene, Wendemagegnehu T. ; Madden, Chris ; Kim, Namhoon ; Lee, Rae-Chang ; Perego, Rich ; Secker, Dave ; Yuan, Chuck ; Vaidyanath, Arun ; Chang, Ken
Author_Institution :
Rambus Inc., Los Altos, CA
fYear :
2008
fDate :
27-29 Oct. 2008
Firstpage :
21
Lastpage :
24
Abstract :
The design and analysis of a Terabyte per second (TB/sec) memory system is presented. The interface technology utilizes a bi-directional low-swing differential signaling with a data transfer rate of 16 Gbps/pair. The memory system uses asymmetrical architecture where the timing adjustment and equalization circuits for both memory WRITE and READ are on the controller to reduce the memory cost. This paper describes the design and analysis employed to develop the memory interface using conventional and low-cost interconnect technologies. The design and characterization of the prototype system at component and system-level are presented and model to hardware correlations are discussed at component and system levels. System analysis is used to optimize and predict the yield of the system, to calculate system timing and voltage margins, and to verify targeted bit-error-rate (BER).
Keywords :
error statistics; integrated circuit design; integrated circuit interconnections; integrated memory circuits; timing circuits; bi-directional low-swing differential signaling; bit error rate; data transfer rate; equalization circuits; interconnect technologies; interface technology; terabyte per second memory system; timing adjustment; Bidirectional control; Bit error rate; Control systems; Costs; Hardware; Integrated circuit interconnections; Prototypes; Read-write memory; Timing; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electrical Performance of Electronic Packaging, 2008 IEEE-EPEP
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-2873-1
Type :
conf
DOI :
10.1109/EPEP.2008.4675866
Filename :
4675866
Link To Document :
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