Compact expressions for period jitter of global binary clock trees

Period jitter plays a critical role in global clock distribution, because it directly impacts the time available for logic operation between sequential elements in the presence of time-varying supply noise. For a given global clock tree topology, the accurate evaluation of period jitter is not only complicated to establish but also exceedingly compute intensive due to its dependency upon many different design parameters. In this paper, we propose a set of analytical expressions which predict period jitter of global clock tree in a fast and accurate manner. A recursive period jitter expression is formulated for global binary clock trees with 32nm rlc interconnects, and it is approximated to a summation based non-recursive expression. Both expressions predict period jitter in the presence of power supply noise with less than 2.93ps error and a speedup of over 100x compared to full-fledged HSPICE simulations The analytical prediction of the worst case period jitter was made possible by the formulation of the non-recursive expression. The worst case period jitter predictions for several different design assumptions closely match the exact worst case period jitter found based on the numerical searches of recursive expression.