DocumentCode
3395714
Title
Automated AC (timing) characterization for digital circuit testing
Author
Balajee, S. ; Majhi, Ananta K.
Author_Institution
Texas Instrum. (India) Ltd., Bangalore, India
fYear
1998
fDate
4-7 Jan 1998
Firstpage
374
Lastpage
377
Abstract
One of the major requirements for testing VLSI devices is the validation of its timing specifications. Timing specifications would typically include frequency, propagation delays, minimum pulse width, phase offsets, setup time and hold time measurements. Although parametric specifications may exist for a nominal speed (frequency) of operation of the digital device, it may be necessary to characterize the device under test (DUT) to determine the highest operating frequency of the DUT and the required environmental parameters to run at the highest frequency. Characterization involves measurement of setup time, hold time and pulse width of the signals. In this paper, we have presented an automated AC (timing) characterization flow for digital circuit testing. We have recommended a STIL (Standard Tester Interface Language) like syntax for the timing tests. Various timing data (setup and hold time, propagation delay etc.) are measured in the first pass of the characterization process and are automatically back annotated to the timing test flow to reduce the total test cycle time. The approach will also help in finding the maximum operating frequency of the DUT and speed binning (i.e., sorting the devices based on their operating frequency)
Keywords
VLSI; automatic testing; integrated circuit testing; integrated logic circuits; logic testing; timing; STIL syntax; Standard Tester Interface Language; VLSI; automated AC timing characterization flow; device under test; digital circuit testing; hold time; operating frequency; phase offset; propagation delay; pulse width; setup time; speed binning; Automatic testing; Circuit testing; Digital circuits; Frequency; Propagation delay; Pulse measurements; Space vector pulse width modulation; Time measurement; Timing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, 1998. Proceedings., 1998 Eleventh International Conference on
Conference_Location
Chennai
ISSN
1063-9667
Print_ISBN
0-8186-8224-8
Type
conf
DOI
10.1109/ICVD.1998.646636
Filename
646636
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