• DocumentCode
    3395737
  • Title

    CMOS circuit simulation using Latency Insertion Method

  • Author

    Sekine, Tadatoshi ; Asai, Hideki

  • Author_Institution
    Dept. of Syst. Eng., Shizuoka Univ., Shizuoka
  • fYear
    2008
  • fDate
    27-29 Oct. 2008
  • Firstpage
    55
  • Lastpage
    58
  • Abstract
    This paper describes the application techniques of latency insertion method to a CMOS circuit simulation. First, the existing and modified application techniques for a CMOS inverter circuit are shown. Then, this method is improved in order to apply to general CMOS circuits. Finally, it is confirmed that our method is useful.
  • Keywords
    CMOS integrated circuits; invertors; CMOS circuit simulation; CMOS inverter circuit; latency insertion method; CMOS technology; Circuit analysis; Circuit simulation; Delay; Electronic circuits; Electronics packaging; Finite difference methods; Inverters; Nonlinear circuits; Systems engineering and theory; CMOS logic circuit; Latency Insertion Method; fast circuit simulation;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electrical Performance of Electronic Packaging, 2008 IEEE-EPEP
  • Conference_Location
    San Jose, CA
  • Print_ISBN
    978-1-4244-2873-1
  • Type

    conf

  • DOI
    10.1109/EPEP.2008.4675875
  • Filename
    4675875
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3395737