Characterization and model of on-chip flicker noise with deep Nwell (DNW) isolation for 130nm and beyond SOC

Author

Yang, M.T. ; Kuo, Darryl C W ; Kuo, C.W. ; Wang, Y.J. ; Ho, Patricia P C ; Yeh, T.J. ; Liu, Sally

Author_Institution

Taiwan Semicond. Manuf. Co., Hsin-Chu, Taiwan

fYear

2005

fDate

4-7 April 2005

Firstpage

125

Lastpage

129

Abstract

An investigation of the flicker noise, by exploring 0.13 μm and beyond MS/RF CMOS technology, was carried out for wireless system-on-a-chip (SOC) applications. The on-chip flicker noise of various components are characterized and accurately modeled. The feasibility of deep N-well isolation to suppress substrate coupling of analog nodes from digital clock noise is also demonstrated.

Keywords

CMOS integrated circuits; flicker noise; integrated circuit measurement; integrated circuit modelling; integrated circuit noise; isolation technology; mixed analogue-digital integrated circuits; radiofrequency integrated circuits; semiconductor device measurement; semiconductor device models; system-on-chip; 0.13 micron; 130 nm; DNW; MS/RF CMOS technology; SOC; analog node substrate coupling suppression; deep N-well isolation; digital clock noise; on-chip flicker noise; wireless system-on-a-chip; 1f noise; CMOS logic circuits; CMOS technology; Crosstalk; Isolation technology; Noise measurement; Phase noise; Radio frequency; Semiconductor device modeling; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures, 2005. ICMTS 2005. Proceedings of the 2005 International Conference on

Print_ISBN

0-7803-8855-0

Type

conf

DOI

10.1109/ICMTS.2005.1452242

Filename

1452242