Title :
Analysis of entire power distribution system of chip, package and board for high speed IO design
Author :
Hsu, Hsing-Chou ; Lin, Jack
Author_Institution :
Azurewave Technol., Taipei
Abstract :
In this paper, the analysis of the power distribution system(PDS), including chip, package and board, was presented for system level design in the high-speed IO application. The integrated-analysis methodology was to link different scale physical geometries in an interactive platform. Instead of using the traditional time-domain simulation, the IO power distribution system characteristics were analyzed through frequency domain impedances, taking into account the coupling of simultaneously switching of adjacent IO cells. Finally, the chip-package-board co-simulation and what-if analysis were carried out for the entire system response optimization.
Keywords :
flip-chip devices; integrated circuit testing; printed circuit testing; chip-package-board co-simulation; frequency domain impedances; power distribution system; system level design; system response optimization; time-domain simulation; Analytical models; Bills of materials; Couplings; Design optimization; Frequency; Geometry; Packaging; Performance analysis; Power distribution; System analysis and design;
Conference_Titel :
Electrical Performance of Electronic Packaging, 2008 IEEE-EPEP
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-2873-1
DOI :
10.1109/EPEP.2008.4675887