DocumentCode :
3396059
Title :
MOSFET matching improvement in 65nm technology providing gain on both analog and SRAM performances
Author :
Difrenza, R. ; Rochereau, K. ; Devoivre, T. ; Tavel, B. ; Duriez, B. ; Roy, D. ; Jullian, S. ; Dezzani, A. ; Boulestin, R. ; Stolk, P. ; Arnaud, F.
Author_Institution :
STMicroelectronics, Crolles, France
fYear :
2005
fDate :
4-7 April 2005
Firstpage :
137
Lastpage :
142
Abstract :
The 65 nm process has been optimized through thermal budget and implant of halo and LDD to reduce gate impact. It provides the best matching results ever reported to our knowledge, i.e. AVt of 2.1 and 1.9 mV.μm for NMOS and PMOS respectively. We demonstrate that such results provide relevant circuit performance improvement. For SRAM, a gain of more than 50% has been achieved on cell read current going from 4 down to 2.1 mV.μm. For analog applications, significant improvement is pointed out in terms of linearity and resolution.
Keywords :
CMOS analogue integrated circuits; CMOS memory circuits; MOSFET; SRAM chips; doping profiles; 65 nm; ADC; CMOS technology; DAC; LDD concentration; MOSFET matching; NMOS; PMOS; SRAM; analog IC linearity; analog IC resolution; cell read current; gate impact reduction; gate process optimization; halo implant; thermal budget; CMOS technology; Fluctuations; Implants; MOS devices; MOSFET circuits; Performance evaluation; Performance gain; Random access memory; Temperature; Threshold voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microelectronic Test Structures, 2005. ICMTS 2005. Proceedings of the 2005 International Conference on
Print_ISBN :
0-7803-8855-0
Type :
conf
DOI :
10.1109/ICMTS.2005.1452247
Filename :
1452247
Link To Document :
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