DocumentCode :
3396220
Title :
Development of a cost-reduced package thru DOE validation and zero-margin design concept
Author :
Kong, Jackson ; Huang, Jimmy ; Quah, Wan Ching ; Beh, Teong Keat
Author_Institution :
Intel Microelectron. (M) Sdn Bhd, FTZ, Bayan Lepas
fYear :
2008
fDate :
27-29 Oct. 2008
Firstpage :
151
Lastpage :
154
Abstract :
As gold price hits record high after record high since the turn of millennium and fast approaching the USD1,000 per ounce barrier, the cost of wirebond package has rocketed high because Gold (99.9%) is the major material for wire bonding. Instead of turning existing chip into using flip chip packaging technology, various cost reduction steps, including package form-factor and wire reduction, are gaining higher priority. Electrical concerns, reliability and product compatibility remain the major key technical challenges. This paper details the engineering hurdles with the new package designed that comes with huge crucial package parameters reduction, and its resolutions thru design of experiment (DOE) experiments and debugging simulation analysis.
Keywords :
ball grid arrays; design of experiments; flip-chip devices; plastic packaging; DOE validation; cost-reduced package; debugging simulation analysis; design of experiment; flip chip packaging technology; package form-factor; package parameters reduction; wire bonding; wire-bonded plastic ball grid array; wirebond package; zero-margin design concept; Aerospace materials; Bonding; Costs; Flip chip; Gold; Packaging; Reliability engineering; Turning; US Department of Energy; Wire;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electrical Performance of Electronic Packaging, 2008 IEEE-EPEP
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-2873-1
Type :
conf
DOI :
10.1109/EPEP.2008.4675900
Filename :
4675900
Link To Document :
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