DocumentCode :
3396395
Title :
Parallel algorithm for analysis of high-speed interconnects
Author :
Paul, D. ; Nakhla, N.M. ; Achar, R. ; Nakhla, M.S.
Author_Institution :
Dept. of Electron., Carleton Univ., Ottawa, ON
fYear :
2008
fDate :
27-29 Oct. 2008
Firstpage :
191
Lastpage :
194
Abstract :
In a system containing high-speed interconnects, the presence of a large number of coupled lines seriously limits the ability to perform fast simulations. In this paper, a parallel algorithm is presented that allows for this class of simulations to be performed efficiently. The proposed method exploits the recently developed algorithm using transverse partitioning and waveform relaxation. A new partitioning algorithm is also proposed to create additional parallelism during transient simulations. In this approach, for a simulation of m lines run on p processors, the computational complexity is O(mp-1). This provides considerable savings as opposed to O(mbeta), 3 les beta les 4 for full coupled-line simulations.
Keywords :
integrated circuit interconnections; computational complexity; coupled-line simulations; high-speed interconnects; parallel algorithm; partitioning algorithm; waveform relaxation; Algorithm design and analysis; Circuit simulation; Computational modeling; Coupling circuits; Differential equations; Frequency; Integrated circuit interconnections; Parallel algorithms; Partitioning algorithms; Time domain analysis;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electrical Performance of Electronic Packaging, 2008 IEEE-EPEP
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-2873-1
Type :
conf
DOI :
10.1109/EPEP.2008.4675911
Filename :
4675911
Link To Document :
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