VHSIC phase 2 test requirements for the depot

Author

Griffin, Ken

Author_Institution

AAI Corp., Hunt Valley, MD, USA

fYear

1989

fDate

25-28 Sep 1989

Firstpage

289

Lastpage

295

Abstract

The recently released Phase 2 very high speed integrated circuits (VHSIC) standards show that VHSIC will operate up to 100 MHz. The author examines the ATE (automatic test equipment) test capability that will be required for these high-performance digital circuits and whether new ATE capability will be required or whether present technology will be sufficient. His analysis shows that using the VHSIC Phase 2 interface buses (PI bus, TM-bus, and ETM-bus) and maximizing the use of system/module/IC built-in-test, a 25-MHz tester can satisfy depot test requirements. In addition, bus interface circuits designed to emulate the internal/external event-driven VHSIC bus protocols at operational speeds facilitate this concept

Keywords

VLSI; automatic test equipment; automatic testing; computer interfaces; digital integrated circuits; integrated circuit testing; maintenance engineering; protocols; standards; 100 MHz; 25 MHz; ATE; ETM-bus; IC testing; PI bus; TM-bus; VHSIC; computer interfaces; depot test; high-performance digital circuits; interface buses; protocols; standards; very high speed integrated circuits; Aerospace electronics; Backplanes; Circuit testing; Clocks; Contracts; Integrated circuit manufacture; Integrated circuit technology; Integrated circuit testing; System testing; Very high speed integrated circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

AUTOTESTCON '89. IEEE Automatic Testing Conference. The Systems Readiness Technology Conference. Automatic Testing in the Next Decade and the 21st Century. Conference Record.

Conference_Location

Philadelphia, PA

Type

conf

DOI

10.1109/AUTEST.1989.81136

Filename

81136