Title :
Controlled impedance chip-to-chip interconnect using coplanar wire bond structures
Author :
Harkness, Samuel ; Meirhofer, Jeffrey ; LaMeres, Brock J.
Author_Institution :
Dept. of Electr. & Comput. Eng., Montana State Univ., Bozeman, MT
Abstract :
This paper presents the design and finite element analysis (FEA) of a controlled impedance chip-to-chip interconnect system using coplanar wire bonds. Our proposed system uses on-chip coplanar transmission lines which interface to 3 adjacent wire bonds configured to yield a fully impedance matched system.
Keywords :
coplanar transmission lines; finite element analysis; integrated circuit design; integrated circuit interconnections; system-in-package; controlled impedance chip-to-chip interconnect; coplanar wire bond structures; finite element analysis; fully impedance matched system; on-chip coplanar transmission lines; system-in-package; Bonding; CMOS technology; Control systems; Coplanar transmission lines; Impedance; Integrated circuit interconnections; Packaging; System-on-a-chip; Transistors; Wire;
Conference_Titel :
Electrical Performance of Electronic Packaging, 2008 IEEE-EPEP
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-2873-1
DOI :
10.1109/EPEP.2008.4675931
