• DocumentCode
    3396741
  • Title

    A fast two-level logic minimizer

  • Author

    Rao, P. Srinivasa ; Jacob, James

  • Author_Institution
    Microelectron. & Comput. Div., ITI, Bangalore, India
  • fYear
    1998
  • fDate
    4-7 Jan 1998
  • Firstpage
    528
  • Lastpage
    533
  • Abstract
    We present NEWMIN, an efficient cube-based algorithm for minimization of single Boolean functions. The salient features of the algorithm are that it does not generate all the prime cubes, and highly efficient heuristics are used do obtain a minimal SPC cover. This leads to savings in computation time and reduces the cost of the solution as well for some classes of functions. The performance of a prototype implementation of NEWMIN is compared to that of ESPRESSO, the best known logic minimizer currently available. Our algorithm efficiently handles Achilles´ heel functions which ESPRESSO finds difficult. Further, as is evident from the results, NEWMIN exhibits better performance on several classes of functions such as parity functions, cyclic functions and most randomly generated functions
  • Keywords
    Boolean functions; VLSI; circuit CAD; integrated circuit design; integrated logic circuits; logic CAD; minimisation of switching nets; Achilles heel functions; NEWMIN; computation time reduction; cube-based algorithm; cyclic functions; fast two-level logic minimizer; parity functions; randomly generated functions; single Boolean functions minimisation; Boolean functions; Costs; Heuristic algorithms; Jacobian matrices; Logic circuits; Logic design; Microelectronics; Minimization methods; Prototypes; Terminology;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design, 1998. Proceedings., 1998 Eleventh International Conference on
  • Conference_Location
    Chennai
  • ISSN
    1063-9667
  • Print_ISBN
    0-8186-8224-8
  • Type

    conf

  • DOI
    10.1109/ICVD.1998.646660
  • Filename
    646660