Bit level VLSI design of high throughput DLMS adaptive IIR filters

In this paper, a novel VLSI design of an adaptive digital filter is presented. Various design techniques, at both algorithm and architecture levels, are employed to achieve the high throughput operations. The delayed LMS adaptation algorithm in conjunction with the non-recursive equation error criterion are adopted to exploit the computing concurrency between the filter and adaptation sections. A distributed arithmetic (DA) based inner product computing scheme is also devised for the bit-level pipelining. The entire design is a modular systolic array with simple control. The VLSI implementation features a 3609×4112 μm² core size with approximate 100,000 transistors. Post layout simulation indicates the resultant 4-tap adaptive IIR filter design can reach a throughput rate as high as 3.3 Msamples per second.