Is there a lag from input to output of a thyristor converter?

Dynamic behavior of thyristor converters has until now been modeled using a fixed-period sampling element, assuming an approximate transport lag of T/sub 0//2. Many experiments have shown that this is longer than the actual lag, and the model needs to be revised. A variable-period sampling model is proposed. Theoretical analysis and simulation results show that the converter should be considered as a proportional element without lag.<>